In the previous post, we learned that combining logic gates like AND, OR, and NOT can build a calculator that performs addition. But this calculator had one major limitation: it cannot remember the results of its calculations.
Circuits like adders, where the output is determined immediately based only on the current input values, are called combinational logic circuits. When the input changes, the output changes right away, and the circuit has no memory of what inputs came before.
It’s like a light switch on the wall that only stays on while you’re pressing it — as soon as you release it, the light goes off. A normal light switch works as a toggle, staying on once pressed and turning off when pressed again, but combinational logic circuits can’t do this because they need to remember the previous state of the light to calculate the new state.
Today, let’s look at the circuit that cures the computer’s amnesia: the sequential logic circuit.
Circuits that have the ability to remember are called sequential logic circuits. Sequential logic circuits determine their output based not only on the current input but also on their previous state (remembered value).
So how do sequential logic circuits remember information? Feedback — a structure where the circuit’s output loops back as its input — is the key. Using this feedback loop, we can build the simplest form of memory device: the SR latch.
A NOR gate is an OR gate followed by NOT — it outputs 1 only when both inputs are 0. An SR latch can be built with just two NOR gates.
You can click S and R to toggle their values. Try the following sequence:
The SR latch has two inputs and two outputs:
| S | R | Q | Q̅ | Action |
|---|---|---|---|---|
| 0 | 0 | Hold previous state | Hold previous state | Hold |
| 0 | 1 | 0 | 1 | Reset |
| 1 | 0 | 1 | 0 | Set |
| 1 | 1 | Unstable | Unstable | Forbidden |
Let’s look at the role of each input and output:
The most important feature is that when both S and R inputs return to 0, the latch continues to hold the value it previously remembered.
The SR latch provides basic “memory” functionality, but it has several problems when used in actual computers.
The biggest problem is the unstable state that occurs when both S and R are 1 at the same time. When both S and R are 1, both NOR gates’ outputs are forced to 0. That is, Q=0 and Q̅=0, which violates the SR latch’s basic definition that “Q and Q̅ always have opposite values.”
An even bigger problem occurs when returning to S=0, R=0 from this state. Both NOR gates receive input 0 simultaneously and enter a race condition where each waits for the other’s output. Depending on which gate responds first, Q could become 1 or 0. The result is unpredictable.
The D latch was developed to solve the SR latch’s problems. The D latch uses AND gates to modify the SR latch’s input circuitry, fundamentally preventing the unstable state where S and R are both active.
You can click D and E to toggle their values. Try the following sequence:
The D latch has just one “Data (D)” input and one “Enable (E)” input.
Only while the Enable (E) signal is on does the Data (D) input’s value get reflected in Q. When the Enable signal is off, no matter how much D changes, the latch holds its previous value.
Think of E as a lock that secures Q.
We’ve built a latch that remembers information by using the feedback structure of logic gates. But the D latch has one remaining limitation. While the Enable signal is on, it follows input changes directly, which means data can propagate unintentionally in systems where multiple latches are connected.
In the next post, we’ll examine this problem in more detail and cover the clock and flip-flop that solve it.